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CD74AC164M

Name: Texas Instruments CD74AC164M
Brand: Texas Instruments
SKU: 595-CD74AC164M
Price: 0.98 EUR
Availability: InStock

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Mouser No:

595-CD74AC164M

Mfr. No:

CD74AC164M

Mfr.:

Texas Instruments

Description:

Counter Shift Registers 8-Bit Ser-In/Prl-Out Shift Register

Lifecycle:

End of Life:

Scheduled for obsolescence and will be discontinued by the manufacturer.

Datasheet:

CD74AC164M Datasheet

ECAD Model:

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In Stock: 128

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Ext. Price:

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Est. Tariff:

Pricing (EUR)

Qty.	Unit Price	Ext. Price
	0,98 €	0,98 €
	0,711 €	7,11 €
	0,602 €	15,05 €
	0,601 €	60,10 €
	0,568 €	568,00 €
	0,542 €	2.168,00 €
	0,501 €	4.008,00 €

Alternative Packaging

Mfr. Part No.:

CD74AC164M96

Packaging:

Reel, Cut Tape, MouseReel

Availability:

In Stock

Price:

0,59 €

Min:

Similar Product

Mfr.:

Texas Instruments

Mfr. No:

CD74AC164M96

Description:

Counter Shift Registers 8-Bit Ser-In/Prl-Out Shift Register A 59 A 595-CD74AC164M

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Texas Instruments
Product Category:	Counter Shift Registers
RoHS:
Counting Sequence:	Serial to Parallel
Number of Circuits:	1 Circuit
Number of Bits:	8 bit
Package/Case:	SOIC-14
Logic Family:	74AC
Logic Type:	CMOS
Number of Input Lines:	2
Propagation Delay Time:	157 ns, 17.5 ns, 12.5 ns
Supply Voltage - Min:	1.5 V
Supply Voltage - Max:	5.5 V
Minimum Operating Temperature:	- 55 C
Maximum Operating Temperature:	+ 125 C
Packaging:	Tube
Brand:	Texas Instruments
Function:	Shift Register
Mounting Style:	SMD/SMT
Number of Output Lines:	8
Operating Supply Voltage:	1.5 V to 5.5 V
Product Type:	Counter Shift Registers
Series:	CD74AC164
Factory Pack Quantity:	50
Subcategory:	Logic ICs
Unit Weight:	129,400 mg

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Product Catalogs

Logic Guide (Rev. AB)

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TARIC:: 8542319000
CNHTS:: 8542319090
CAHTS:: 8542390000
USHTS:: 8542390090
KRHTS:: 8542311000
MXHTS:: 8542310399
ECCN:: EAR99

CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers

Texas Instruments CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers have two serial inputs (A and B) connected through an AND gate and an asynchronous clear (CLR). The device requires a high signal on both A and B to set the input data line high; a low signal on either will set the input data line low. Data at A and B can be changed while CLK is high or low, provided the minimum set-up time requirements are met.