SN65DSI84/SN65DSI84-Q1 DSI to FlatLink Bridge

Texas Instruments SN65DSI84/SN65DSI84-Q1 DSI to FlatLink™ Bridge features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1Gbps per lane and a maximum input bandwidth of 4Gbps. The bridge decodes MIPI DSI 18bpp RGB666 and 24bpp RGB888 packets. The device also converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25MHz to 154MHz, offering a Dual-Link LVDS with four data lanes per link. The SN65DSI84/SN65DSI84-Q1 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces. The Texas Instruments SN65DSI84-Q1 devices are AEC-Q100 qualified for automotive applications.