Microchip Technology PIC32CM SG00/GC00 32-Bit Arm® Cortex®-M23 MCUs

Microchip Technology PIC32CM SG00/GC00 32-Bit Arm^® Cortex^®-M23 Microcontrollers (MCUs) are a family of low-power 32-bit Arm-based MCUs that offer security, safety, CAN-FD, full-speed USB, enhanced touch, and advanced analog features. The Arm Cortex-M23 CPU can run up to 72MHz and has a 2.64 CoreMark/MHz and 1.03 DMIPS/MHz rating. Security features include the Arm TrustZone^® and Device Identity Composition Engine (DICE) support. It also has a Hardware Security Module (HSM Lite) and TrustRAM. The Microchip Technology PIC32CM SG00/GC00 advanced analog features include a 12-bit Analog-to-Digital Converter (ADC) module with up to 4.5Msps, up to 12 single-ended channels, or three differential and six single-ended channels. The enhanced peripheral touch controller has up to 324 (18 x 18) mutual capacitance channels and up to 36 self-capacitance channels with Driven Shield+ technology. These devices are available in TQFP-48, VQFN-48, TQFP-64, VQFN-64, or TSFP-100 packages.

Features

Operating conditions
- 1.71V to 3.63V, -40°C to +125°C, DC to 48MHz
- 1.71V to 3.63V, -40°C to +85°C, DC to 72MHz
Arm Cortex-M23 core CPU running at up to 72MHz
- 2.64 CoreMark/MHz and 1.03 DMIPS/MHz
- Nested Vector Interrupt Controller (NVIC)
- Stack limit checking
- Memory Protection Unit (MPU)
Memories
- An additional 16KB of Boot Flash Memory (BFM)
- An additional 32KB of Configuration Flash Memory (CFM)
- Flash supports
  - Error Correction Code (ECC) with fault injection capability
  - CRC of any contiguous section
  - Deep power down option while the system is in standby
  - In-band error reporting for both read and write accesses
  - Tamper event logging
- 128KB SRAM main memory with ECC and fault injection capability, retained in idle, standby, and hibernate modes
- 512bytes TrustRAM
Security features
- Arm TrustZone technology for flexible hardware isolation of memories and peripherals
  - Configurable partitioning of PFM, BFM, SRAM
  - Individual security attribution for each peripheral, I/O, and external interrupt line
- Secure boot (optional)
- Device Identity Composition Engine (DICE) support
- Physical Unclonable Function (PUF) generates a device unique key for local encryption and attestation
- Hardware Security Module (HSM Lite)
  - AES (256 bits), SHA-1, SHA-2, RSA, ECC accelerator
  - True random number generator
- TrustRAM
Advanced analog features and touch
- 12-bit ADC module
  - Up to 4.5Msps
  - Up to 12 single-ended channels or three differential and six single-ended channels
  - External reference support
- Two analog comparators with programmable voltage references
- Enhanced Peripheral Touch controller (PTC)
  - Up to 324 (18 x 18) mutual capacitance channels
  - Up to 36 self-capacitance channels with Driven Shield+ technology for better noise immunity and moisture tolerance
  - Low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, and wheels
  - Hardware noise filtering and noise signal desynchronization for high conducted immunity
  - Supports wake-up on touch from standby sleep mode
  - Supports a large self-capacitor sensor
System
- Integrated Power-on Reset (POR) and programmable Brown-out Detection (BOD) on VDDIO and VDDREG
- Programmable Low-Voltage Detect Module (LVD)
- 12-channel event system for inter-peripheral core-independent operation (EVSYS)
- Unique 128-bit serial number
Hardware safety features
- ECC with fault injection capability on Flash and SRAM
- SRAM/TrustRAM MBIST in boot user mode is accessible
- IP registers write protection through PAC
- Fail-Safe Clock Monitor (CFD)
- ISO 26262:2018 compliant
Power management
- Idle mode for fast wake-up time
- Standby mode, backup mode, off mode, and sleep walking peripherals
- Hibernate mode up to full SRAM retention

Timers/output compare/input capture
- Up to seven 16-bit Timer/Counters for Control (TCC), each with two double-buffered compare/capture channels
- 32-bit Real-Time Counter (RTC) with clock/calendar functions
- Watchdog Timer (WDT) with window mode
Clock management
- 4MHz to 48MHz crystal oscillator (XOSC48), clock failure detection with a safe clock switch
- 32.768kHz crystal oscillator (XOSC32K), clock failure detection with a safe clock switch
- 32.768kHz ultra low-power internal RC oscillator (OSCULP32K)
- 48MHz digital phase-locked loop (DFLL48M)
- 1.6GHz phase locked loop (PLL1G6)
- Frequency meter (FREQM)
Software and tools support developing prototypes quickly with a powerful, easy-to-use ecosystem
- Get code off to a head start with MPLAB Code Configurator
- Graphically configure peripherals, software libraries, and supported RTOS with MPLAB Harmony v3
- Download MPLAB XC Compiler
- Take advantage of MPLAB X IDE’s support for 32-bit MCUs
- Select the ideal debugger for the project (MPLAB^® ICE, MPLAB ICD, or PICkit™)
Direct Memory Access (DMA)
- Eight channels with four different block transfer modes
- Programmable 32-bit Cyclic Redundancy Check (CRC)
Input/output
- High current pins with up to 25mA source/sink
- Configurable open-drain output on digital I/O pins
- Up to 10 5V-tolerant input pins (digital pins only)
- Up to 80 programmable I/O lines
- 16 external interrupts (EIC)
- Two Configurable Custom Logic (CCL) that supports
  - Combinatorial logic functions, such as AND, NAND, OR, and NOR
  - Sequential logic functions, such as flip-flops and latches
- One general-purpose Low Drop-Out (LDO) output
  - 1.2V/1.5V/1.8V/2.5V generated from VDDIO
  - Up to 100mA
- Two outputs controlled by SUPC
Communication interfaces/digital peripherals
- Two CAN-FD modules (ISO 11898-1:2015), supports CAN 2.0 A/B
- Six Serial Communication Interfaces (SERCOM), each configurable to operate as
  - USART with full-duplex and single-wire half-duplex configuration
  - I²C host/client up to 3.4MHz
  - SPI
  - RS-485, IRDA, LIN host/client
- One Full-Speed (12Mbps) Universal Serial Bus (USB) 2.0 interface
  - Embedded host and device function
  - Eight endpoints
  - On-chip transceiver with integrated serial resistor
  - Supports crystal-less operation in device mode
AEC-Q100 Grade 1 qualified (-40°C to +125°C)
Debugger development support
- In-circuit and in-application programming/debugging with SWD and JTAG
- Cortex-M debugger port
- Supports eight breakpoints and four watch points
- IEEE^®1149-compatible (JTAG) boundary scan
- Non-intrusive hardware-based instruction trace, secure debugging